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IBM Delivers With POWER8


POWER8 technology created some buzz when it was first discussed at the Hot Chips conference and slides that describe the chips could be found online before today. But now we have more information about the actual systems that will be shipping when they become generally available in June.

When you look at the Power Processor Technology Roadmap since 2004, you can see that we regularly get new, more powerful chips. We are almost spoiled. When IBM says it is going to deliver, it does just that, with both new hardware and new OS releases.

In 2004 we had POWER5 followed by POWER5+. In 2007 we had POWER6, which led to POWER6+. In 2010 we had POWER7 and the most current, POWER7+. In 2014 we have POWER8, and there are already charts that show POWER9 is being planned for the future. IBM has consistently delivered on its roadmaps.

I recently attended an education session for IBMers and business partners that covered information around POWER8 and the new IBM hardware announcements that are being made today. I am going to hit some of the highlights, but additional information will be included in future posts.

The POWER8 Chip

The POWER8 chip is another step up from what has come before. We have gone from four threads to eight threads per core. With simultaneous multithreading (SMT) enabled you can have up to eight threads running on a core, which means you can get more work done per CPU cycle.

The charts that I saw showed a linear increase in the number of transactions that could be completed when you compared SMT1 to SMT2 to SMT4 to SMT8. As you made each transition you could see the number of transactions increase. Obviously some workloads won’t benefit from SMT, but those will be the exception rather than the rule.

I also saw charts that compared I/O bandwidth and memory bandwidth on the new systems compared to older models, and the numbers were impressive. It was a significant increase that I will be discussing further in future articles.

While POWER7 technology had up to eight cores per socket, the POWER8 chip has up to 12 cores per socket. New memory controllers and memory cache on the system improve memory latency and performance.

The way the cores communicate with one another across the SMP interconnect has also improved so it takes less “hops” to go from one core to another in the system. The chip also boasts a direct PCIe Gen3 I/O interface for incredible bandwidth.

There is 512 K L2 cache per core, 96 MB shared L3 cache and up to 128 MB L4 off-chip cache.

Rob McNelly is a Senior AIX Solutions Architect for Meridian IT Inc. and a technical editor for IBM Systems Magazine. He is a former administrator for IBM. Rob can be reached at rob.mcnelly@gmail.com.





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