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New IBM z13 Chip Improves Throughput and Analytics Performance

In April 2014, the IBM mainframe celebrated its 50th anniversary, showcasing a computing platform that continues to reinvent itself by incorporating new technologies and capabilities. To continue that tradition, the newest mainframe, IBM z13*, was announced in January, signifying a new generation of machines that will continue for the next 50 years.

The z13 system includes many new features and innovations to help clients with computing tasks related to cloud, mobile, analytics and security. It features a new microprocessor chip that is manufactured with IBM’s 22 nanometer Silicon-on-Insulator (SOI) technology, allowing close to 4 billion transistors on chip, nearly 45 percent more than its predecessor, the IBM zEnterprise* EC12 (zEC12).

This higher density technology enables 100 percent more level 2 (L2) and 30 percent more level 3 (L3) caches on chip. The shared 64 MB of on-chip L3 caches is shared among up to 10 microprocessor cores, two more than zEC12, allowing up to 141 configurable cores within the system. Each core is extensively re-engineered to provide traditional performance gains and new capabilities.

Here, we will discuss two of the major features introduced in z13: simultaneous multithreading (SMT) that drastically improves overall computing throughput with minimal increase in power consumption, and a single instruction, multiple data (SIMD) instruction set architecture that significantly enhances analytics analysis performance.

SMT for Efficiency

The z13 core supports up to two software threads running simultaneously within its processing pipeline, commonly known as two-way multithreading (SMT2). Modern processor cores are superscalar, meaning multiple stations at any pipeline stage perform similar tasks. For example, in z13 up to 10 instructions can be issued to the 14 different execution units.

Often, a single program thread is not able to make use of the available processing capacity, likely due to instruction dependencies (e.g., waiting for a divide operation that might take six cycles) or cache misses (where the data is located more than 40 cycles away in the L3 cache). Another thread running concurrently allows the processor to work on one thread’s instructions while another thread is stalled. The z13 core alternates between and mixes up the instruction processing requirements between the two threads, achieving high throughput gain by sharing and managing its “spare” capacities efficiently.

The z13 core consists of multiple processing units and stages. The front end consists of the “branch prediction” (IFB) unit, the “instruction fetching and caching” (ICM) unit and the “instruction buffer, queuing and decoding” unit (IDU) that process instructions in program order. The instruction issue unit (ISU) and the execution units process instructions out of program order.

Brian Curran is a Distinguished Engineer in IBM Systems working in the development of z Systems microprocessors.

Eric Schwarz is a Distinguished Engineer in IBM Systems working in the development of z Systems microprocessors.

C. Kevin Shum is a Distinguished Engineer in IBM Poughkeepsie’s System and Technology Group, working in the development of System z microprocessors.



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