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Is Computer Hardware Underappreciated?

November 19, 2018

Last week, I asked the question, “What software engineer doesn’t have a healthy respect for the hardware?” My thought was that respect is one thing, but understanding it is another. This week, I’ll explore a few features imbedded (maybe hidden to the software engineer) in the machine that is the IBM z14. Can we really explore this cosmic topic in a post? Maybe if we break it down into a few main points and focus just on them. Let’s see.

IBM z14
When I attended the Enterprise Computing Community Conference this past June at Marist College, I picked up a index card-like document that contained shorthand details on the hardware characteristics. For the z14 Models M01-05, it reads:

SCM: up to six per drawer
  • CMOS 14SO 14nm SOI technology
  • 17 layers of metal6.1 billion transistors
  • 14.4 miles of copper wire
  • Up to 10 active cores (PUs) per chip/up to 170 configurable cores
    • 5.2 GHz
    • L1 cache/core
      • 128 KB I-cache
      • 128 KB D-cache
    • L2 cache/core
      • 4M + 2M Byte eDRAM split private L2 cache
  • L3 cache on chip
    • 128 MB eDRAM shared by all cores
    • Enhanced Instructions for single instruction/multiple data (SIMD)
    • Single thread or next generation two-way simultaneous multithreading (SMT) operation
    • Five clock domains
The document contained dense shorthand, including more than a dozen acronyms used by an IBM representative as talking points during a brief conversation with an attendee. There is a lot of detail available on the web to explore this shorthand.

SCM and CMOS Discussed
The document contained the acronym “SCM,” which refers to “single chip module.” This is the packaging of a chip with all the needed support circuits, on a card. Chips might be a central processor (CP) chip, depicted as “CP SCM” or a system control (SC) chip, like “SC SCM.” It’s useful to have this SCM as a packaging approach to have elements that fit well into drawers. Also, this approach helps to keep the modules cool during operation, as one SCM per card simplifies this challenge somewhat.

The IBM z14 document also references CMOS, which refers to “complementary metal-oxide semiconductor.” CMOS is a proven technology that has a number of desirable characteristics. It has high input impedance, the outputs actively drive both ways, the outputs are pretty much rail-to-rail, CMOS logic consumes very little power when held in a fixed state and CMOS gates are very simple as the basic gate is a inverter, which is only two transistors. This simplicity along with the low power consumption means CMOS lends itself well to dense integration. Looked at another way, you get a lot of logic for the size, cost and power.  

SIMD and Cache Enhancements
The IBM z14 document also references “enhanced single instruction/multiple data” (SIMD). SIMD was introduced in z13 and enhanced in z14 with new instructions. These instructions, part of a new decimal arithmetic SIMD engine, were designed to boost COBOL, PL/I code and analytics applications.

“Cache” appears several times in the document. For example, there’s L1 and L2 cache. Cache is a very important element because this computer memory is used to hold data that’s operated on by instructions. Changes over time in cache size and operation have been mainly designed to reduce unproductive cycles spent waiting for data to be staged for operation. This topic is discussed in detail in a series of posts and elsewhere on the web.

In this ongoing effort to improve cache operation, the z14 has a new directory design that better integrates the different levels of cache and makes more efficient use of power. Specifically, L1 cache increased to 128 KB/core from 96 KB/core (a 33 percent increase) while L2 cache increased to 4 MB/core from 2 MB/core; (a 100 percent increase) and L3 cache increased to 128 MB/CP from 64 MB/CP (a 100 percent increase). Also, a new 672 MB drawer of shared L4 cache is now deployed.

Exploring Teaches You Something New
Writing as a software engineer, when you start exploring specific aspects of the z14 design and improvements, you begin to discover the challenges that the hardware community has been seeking to address through changes in each new release. SCM and CMOS are like building blocks that reflect years of analysis and development whereas cache is generally a more active area of exploration for improvement. Traditional L1 cache directory and z14 enhancements are outlines in a presentation called IBM z14 microprocessor chip set and architectural enhancements. I’ll finish up this topic next week as there are few other areas of z14 that I want to explore and write about. 

Posted November 19, 2018| Permalink