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POWER9 Media Coverage

September 13, 2016

Last month's Hot Chips conference generated quite a bit of press about the soon to be available POWER9 processors:

Intel has the kind of control in the datacenter that only one vendor in the history of data processing has ever enjoyed. That other company is, of course, IBM, and Big Blue wants to take back some of the real estate it lost in the datacenters of the world in the past twenty years.

The POWER9 chip, unveiled at the Hot Chips conference this week, is the best chance the company has had to make some share gains against X86 processors since the POWER4 chip came out a decade and a half ago and set IBM on the path to dominance in the RISC/Unix market.

As it turns out, IBM will be delivering four different variants of the future POWER9 chip, as Brian Thompto, senior technical staff member for the Power processor design team at the company, revealed in his presentation at Hot Chips. There was only one POWER7 and one POWER7+, with variants just having different cores and caches activated. There were three POWER8 chips, one with six cores aimed at scale out workloads and with two chips sharing a single package and one single-die, twelve-core chip aimed at bigger NUMA machines; this year saw the launch of the POWER8 chip (not a POWER8+ even though IBM did call it that for some time) with twelve cores with the NVLink interconnect from Nvidia woven into it.

With the POWER9 chip, there will be the POWER9 SO (short for scale out) variant for machines aimed at servers with one or two sockets, due in the second half of 2017, and the POWER9 SU (short for scale up) that will follow in 2018 for machines with four or more sockets and, we think, largely sold by IBM itself for its customers running its own AIX and IBM i operating systems.

The four versions of the POWER9 chip differ from each other in terms of the number of cores, whether or not the systems have directly attached memory or use the “Centaur” memory buffer chips, and level of simultaneous multithreading available for specific server configurations... .

The twist on the SMT level is the new bit we did not know, and we also did not know the core counts that would be available on the POWER9 SU variants. We knew that the POWER9 SO chip would have 24 cores, and by the way, Thompto tells The Next Platform that the POWER9 SO chip is a single die chip with 24 cores. The POWER9 SU chip will top out at twelve cores, just like the biggest POWER8 chip did. Both POWER9 chips have eight DDR memory ports, each with its own controller on the die, which now can either talk directly to two DDR memory sticks on the POWER9 SO or to a Centaur buffer chip that in turn talks to four DDR memory sticks each.

This ChannelWorld article notes that greater throughput is expected:

Each NVLink 2.0 lane in the POWER9 chip will communicate at 25Gbps (bits per second), seven to 10 times the speed of PCI-Express 3.0, according to IBM. POWER9 will have multiple communication lanes for NVLink 2.0, and they could provide massive throughput when combined.

Recent Nvidia GPUs like the Tesla P100 are based on the company's Pascal architecture and use NVLink 1.0. The Volta GPU architecture will succeed Pascal, also used in GPUs like the GeForce GTX 1080.

With a tremendous bandwidth improvement in over its predecessor, the NVLink 2.0 technology will be important for applications driven by GPUs, like cognitive computing. is intrigued by POWER9's acceleration strategy:

Across a range of benchmarks, POWER9 should deliver from 50% to more than twice the performance of the POWER8 when the new chip arrives late next year, said Brian Thompto, a lead architect for the chip. New core and chip-level designs contribute to the performance boost.

The diversity of choices could help attract OEMs. IBM has been trying to encourage others to build Power systems through its OpenPower group that now sports more than 200 members. So far, it’s gaining most interest from China where one partner is making its own Power chips.

Use of standard DDR4 DIMMs on some parts will lower barriers for OEMs by enabling commodity packaging and thus lower costs.

POWER9’s acceleration strategy is perhaps the most interesting aspect of the new chip.

It will be one of the first microprocessors to implement the 16 GTransfer/second PCI Express Gen 4 interconnect that is still awaiting approval of a final spec. Separately, it implements a new 25 Gbit/s physical interconnect called IBM BlueLink.

Both interconnects support 48 lanes and will accommodate multiple protocols. The PCIe link will also use IBM’s CAPI 2.0 to connect to FPGAs and ASICs. BlueLink will carry the next generation NVLink co-developed for Nvidia GPUs as well as a new CAPI.

eWeek mentions the OpenPower Foundation:

"We want people to know there is an alternative to x86 chips and that alternative can bring a lot of performance with it," Dylan Boday, IBM Power engineer, told eWEEK last week standing outside of the Moscone Center, home to IDF. "At the end of the day, most people want choice, but they also want to see advantages to that choice."

IBM traditionally had developed Power chips to run only in its Power servers. However, the company three years ago—with such partners as Nvidia and Google—launched the OpenPower Foundation, enabling third parties to license the architecture to create their own Power-based systems. It was part of a larger effort to embrace open technologies—such as Linux, OpenStack and the Open Compute Project (OCP)—for its Power architecture.

The work is paying off, according to IBM officials. At the first OpenPower Summit last year, the group had about 130 members. That has since grown to more than 200. At the same time, there are more than 2,300 applications that run on Linux on Power, they said.

As much as I love working with POWER8, I'm already excited for POWER9. (To be honest, I'm even looking forward to the day when I can help customers upgrade to POWER12.) The point is, the future looks bright for the POWER platform.

Posted September 13, 2016| Permalink